1. Field of the Invention
The present invention relates to CMOS integrated circuits and, more particularly, to CMOS circuits which can adapt their speed/power dissipation tradeoff to design conditions.
2. Description of the Related Art
In recent years complementary metal-oxide semiconductors (CMOS) technology has been widely used for VLSI design. The advantage of CMOS technology is that it has very low power dissipation in comparison with other technologies such as bipolar devices. The disadvantage of CMOS technology is that its performance is slow compared to bipolar devices.
As a result of this disadvantage of CMOS technology, BiCMOS technology was developed. BiCMOS technology largely retains the low power dissipation of CMOS technology, yet performs with the high speed of bipolar devices. However, the BiCMOS solution is considerably more complex to fabricate because of the presence of the bipolar devices.
Another problem of BiCMOS technology is that the scalability of this technology at supply voltages of 2 volts or less is a problem. Today, supply voltages of 5 volts and 3.3 volts are most common, but it is thought that the supply voltage could eventually drop to about 1 volt. Hence, the high speed and relatively low power dissipation of BiCMOS is not likely to be available for supply voltages below 2 volts. One attempted solution to the scalability problem of BiCMOS is found in U.S. Pat. No. 5,132,567 which discloses a BiCMOS NAND circuit that apparently provides improved scalability by employing low threshold n-channel FET transistors in conjunction with standard threshold n and p channel FET transistors. The resulting BiCMOS NAND circuit is even more complex to fabricate than conventional BiCMOS.
It is known that higher drive current and faster performance can be obtained by making the cell size of MOS transistors on an integrated circuit larger. However, although increasing the cell size improves switching performance of the given cell, it also undesirabiliy increases the input gate capacitance of the cell which slows the driving of this cell, and requires additional die area which limits chip density.
Conventionally, in the design of integrated circuits, the threshold voltages of the MOS transistors are intentionally made the same magnitude. A threshold voltage is the voltage required to put the transistor in a conductive state. It is defined as that gate-to-source voltage below which only leakage current flows. The threshold voltage of a transistor is controlled or determined by the doping profile of its gate-channel. Typically, with silicon transistors, the threshold voltage is about 0.7 volts. If the source of the transistor is not grounded, the threshold voltage is also effected by the voltage applied to the source voltage. This is known as the body effect of a field effect transistor.
It has recently become known that an entire integrated circuit can be constructed using low threshold voltages for its MOS transistors. See Kitsukawa, "256Mb DRAM Technologies for File Applications", IEEE International Solid-State Circuits Conference, February 1993. The use of low threshold voltages enables the integrated circuit to operate at high speed. The disadvantage with using all low threshold MOS transistors is that power dissipation substantially increases.
Only in a few isolated special situations have MOS transistors with distinctly different threshold voltages have been intentionally placed on the same integrated circuit. For example, U.S. Pat. No. 5,150,186 discloses a CMOS output circuit which adds a zero threshold transistor to an otherwise conventional CMOS transistor pair to prevent damage to the PMOS transistor when high voltages are applied to the output node. U.S. Pat. No. 5,150,186 discloses a similar CMOS driver for the same or similar purpose. These designs are merely protection mechanisms that not only do not improve switching performance of the CMOS circuit but also consume greater die area.
Thus, there is a need for a technology that can provide high speed operation and low power dissipation over a wide range of supply voltages extending approximately from 1 to 6 volts. The technology should support high density circuit designs without significantly complicating the fabrication process.